General Purpose Digital Signal Processing Vme-module for 1-turn Delay Feedback Systems of the Cern Accelerator Chain

In the framework of the LHC project the concept has been developed of a global digital signal processing unit (DSPU) that implements in numerical form the architecture of low-level RF systems [1]. The approach, using an FPGA as core for the low-level system, is very flexible and allows the upgrade of the signal processing by modification of the original firmware [2]. The achieved performances of the LHC 1-Turn delay Feedback are compared with project requirements. The PS Transverse Damper DSPU, with automatic loop delay compensation adapting to the beam’s time of flight and Hilbert Filter for single pick-up betatron phase adjustment, is presented. A modified DSPU with digital inputs for the LHC Transverse Damper is also presented.